1. Field of the Invention
The present invention relates to arithmetic modules, devices and systems, and, more particularly, to an arithmetic module, device and system for digital signal processors.
2. Description of Related Art
With the rapid development of mobile devices in the electronics industry, thin, lightweight and high performance electronic products are under demand. However, with the decreasing size of the mobile devices, the battery capacity is also reduced. Therefore, reducing the power consumption of electronic components in mobile devices to extend battery life has become an important subject.
Moreover, due to the increasingly shorter life cycle of today's electronic products, programmable core circuits that enable most system functionalities to be realized as software and allow designers to readily adjust the functions through the flexibility of the software, which increases the repeated utilization rate as well as shortens the design period, are also the current trend of electronic products. For example, a digital signal processor (DSP) is a programmable general-purpose processor that has an instruction set and architecture designed specifically for digital signal applications.
However, conventional DSPs employ scalar or multi-issue processors. Scalar processors have poor computation performance because they can only process one instruction at a time. If one wishes to raise the computation performance of the scalar processors, increases in the footprint or the power consumption become an issue. On the other hand, multi-issue processors arrange computation units in parallel, which perform computation in parallel, so each instruction has a shorter computation period. However, complexity in the hardware of the input and output ends of the multi-issue processors increases accordingly. For example, in a Very Long Instruction Word (VLIW) processor, for N arithmetic units, the input and output ports of their registers will cause the footprint and delay to increase proportionally by N3 and N3/2.
Therefore, how to improve the arithmetic modules of the digital signal processors in order to reduce power consumption has become a subject in this field ready to be solved.